This invention relates generally to the field of digital communications. Accomplishing digital communication between synchronous systems of unequal clock frequency is difficult. For instance, in a parallel processing network it is necessary that computers with synchronous components be able to communicate with each other. However, in such a network, each processor may have a unique maximum clock frequency that also differs from the maximum clock frequency of the communication network. Communication can be arranged by clocking all processing units at the frequency of the slowest processor. However, this is a poor compromise because maximum performance is only realized by clocking every processing unit at its own maximum frequency.
One approach that has been used for arranging communication between systems having unequal clock frequency is to treat the systems as if they are asynchronous. However, because each of the target systems is ultimately synchronous, probabilistic methods such as synchronizing flip-flops with delayed results must be used to resolve metastable states. This results in imperfect reliability and significant overhead latency.
Another technique that has been used to facilitate communication between synchronous systems of unequal clock frequency is to use an adjustable delay line for selectively adjusting data signals to compensate for uncontrollable phase discrepancies. A disadvantage of this approach is that complex hardware is required.
Other techniques have used shift registers to synchronize the synchronous systems of unequal clock frequency. However, a disadvantage of this approach is that there is a tradeoff between failure rate and propagation delay. More specifically, low synchronization failure rates imply long propagation delays which seriously degrade the performance of the systems.